In the manufacture of integrated circuits, copper interconnects are generally formed on a semiconductor substrate using a copper damascene process (e.g., a dual damascene process which is well known in the art). In this process, a trench is etched into a dielectric layer and the trench is filled with a barrier layer, an adhesion layer, and a seed layer. For instance, a physical vapor deposition (PVD) process, such as a sputter process, may be used to deposit a tantalum nitride barrier layer and a tantalum adhesion layer (i.e., a TaN/Ta stack) into the trench. This may be followed by a PVD sputter process to deposit a copper seed layer into the trench. An electroplating process is then used to fill the trench with copper metal to form the interconnect.
As device dimensions scale down, the aspect ratio of the trench becomes more aggressive as the trench becomes more narrow. This gives rise to issues in the copper seed deposition and plating processes such as trench overhang, thereby resulting in pinched-off trench openings and inadequate gapfill. One approach to addressing these issues utilizes electroless deposition processes to deposit copper into the narrow trenches. Electroless deposition processes permit copper seed or copper gapfill deposition directly on the TaN/Ta stack. Eliminating the metal seed layer widens the available gap for subsequent metallization.
Reducing the thickness of the TaN/Ta stack is another approach to widening the available gap for metallization. In known processes, the Ta adhesion layer is required because metals deposited using conventional vapor deposition processes do not readily nucleate on the TaN barrier layer, leading to problems such as film delamination or agglomeration. Unfortunately, thinner films of TaN/Ta that have been evaluated are limited by the non-conformal characteristic of PVD deposition techniques. Accordingly, alternative techniques for reducing the thickness of the TaN/Ta stack are needed.